CODEWITHSUNDEEP
verilogmultiplication
Lorenzi
Lorenzi

Reputation: 13

Multiplication Issues in Verilog

I'm trying to take two 7-bit numbers and multiply them with Verilog. However, I seem to be running into trouble. The multiplication seems to work (producing an output of 1) when the results are between 0-9 decimal. However it appears that any result larger than 9 does not seem to produce an output of 1. Even though "Operand1" and "Operand2" are technically only 4-bits (0-9 decimal), I've tried switching them to 7-bit numbers to determine if that would solve the issues I'm encountering.

This particular module checks the answer provided by a user in binary through physical switches and returns a 0 if said answer is incorrect and a 1 if correct. All other operations (Addition, Subtraction and Division) work perfectly.

Here is my code:

module checkAnswer(OpSel, negFlag, Operand1, Operand2, usrAnswer, Correct);

input [1:0]OpSel;
input [6:0]Operand1, Operand2;
input negFlag;
input [6:0]usrAnswer;
output reg Correct;

always @ (*)
   case (OpSel)
   2'b00: 
        if ((Operand1%10 + Operand2%10) == usrAnswer)
        Correct = 1'b1;
    else
        Correct = 1'b0;
2'b01:
    if ((negFlag && (Operand2 > Operand1) && ((Operand1%10 - Operand2%10) == -1*usrAnswer)) || ((Operand1 >= Operand2) && ((Operand1%10 - Operand2%10) == usrAnswer)))
        Correct = 1'b1;
    else
        Correct = 1'b0;
2'b10:
    if ((Operand1%10 * Operand2%10) == usrAnswer)
        Correct = 1'b1;
    else
        Correct = 1'b0;
2'b11:
    if ((Operand1%10 / Operand2%10) == (usrAnswer))
        Correct = 1'b1;
    else
        Correct = 1'b0;

     default: Correct = 1'b0;
endcase

endmodule

Upvotes: 1

Views: 854

Answers (1)

toolic
toolic

Reputation: 61937

The problem is caused by operator precedence. Since % and * have the same precedence, your code executes as if parentheses were used like this:

((Operand1%10) * Operand2)%10

If you use 12 and 7, you get 4 instead of 14. To fix it, add more parentheses:

if (((Operand1%10) * (Operand2%10)) == usrAnswer)

Refer to IEEE 1800-2012, 11.3.2 Operator precedence

Upvotes: 2

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