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epsilon_j
epsilon_j

Reputation: 335

Simulating VHDL 2008 unconstrained array type in Vivado 2017.1

I have the following type

type VECTOR_ARRAY_TYPE is array(natural range <>) of std_logic_vector;

which I use in my entity as follows:

entity mux is

  generic (
    sel_width  : positive := 2;
    data_width : positive := 3
  );

  port (
    d   : in  VECTOR_ARRAY_TYPE(2**sel_width - 1 downto 0)(data_width - 1 downto 0);
    sel : in  std_logic_vector(sel_width - 1 downto 0);
    q   : out std_logic_vector(data_width - 1 downto 0)
  );

end mux;

I am using Vivado 2017.1 and have marked the files as VHDL 2008. The files synthesize perfectly well, but I get the following error when trying to Run Simulation:

ERROR: [XSIM 43-4187] File "/project_dir/sources_1/new/alu_data.vhd" Line 42 : The "Vhdl 2008 Unconstrained Array Type as Subtype in Array Type Definition" is not supported yet for simulation.

The line number it is referring to is the type definition above.

Is it the case that the error is correct, and that unconstrained array types cannot be used for simulation? Or is there a setting somewhere which I need to change to configure the simulator differently?

Thanks.

Upvotes: 3

Views: 2628

Answers (1)

JHBonarius
JHBonarius

Reputation: 11261

So your question is about a software tool, which has an extensive on-line documentation. So you should look on the website. http://www.xilinx.com --> support --> documentation --> Development tools --> Hardware development --> Vivado Design Suite --> User Guides. Et voila: UG900 - Vivado Design Suite User Guide: Logic Simulation v2017.4

Appendix C: VHDL 2008 Support in Vivado Simulator

The Vivado® simulator supports the subset of VHDL 2008(IEEE 1076-2008). The complete list is given in Table C-1.

[partial] Table C-1:

  • VHDL-2008 STD and IEEE packages precompiled, including new fixed and float packages, unsigned bit etc.
  • Simplified sensitivity list
  • Matching Relational Operators
  • Unary Reduction Logic Operators
  • Simplified Case Statement
  • Array / Bit Logic Operators
  • Array / Bit Addition Operators
  • Enhanced Bit String Literals
  • Conditional and selected sequential statements
  • Protected type
  • Keyword ‘parameter’ in procedure declaration
  • Array element resolution function in subtype definition
  • Block comments
  • Predefined array types
  • Type passed as Generic
  • Hierarchical references to signal
  • Expression in port map
  • Reading output port

Note: Other features that are not mentioned in the above table, are not supported by Vivado Simulator.

Upvotes: 3

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