CODEWITHSUNDEEP
branchintelpredictionamd-processor
Peter
Peter

Reputation: 2320

Impact of disabled branch prediction on AMD Ryzen, regarding SPECTRE

AMD states here that the are not affected by Meltdown (i.e. Variant 3), likely not by Variant 2 but by Variant 1 (both SPECTRE). Therefore AMD has released an Microcodeupdate for FAM 17H (i.e. Ryzen) and switched OFF branch prediction. What kind of branch prediction is here turned OFF?

Sadly I only own a mobile SandyBridge* and an AMD Phenomen X4 905e (the updated microcode is only for Ryzen). Can some execute benchmarks like here with a sorted array?
The mentioned update from SUSE just speaks about branch prediction which could mean either Variant 1 (if/else) or Variant 2 (branch jump buffer). Also the people from Google use the term branch prediction for Variant 1 and Variant 2. So it is ambigious what actually was turned OFF.

Why should AMD turn OFF Variant 2 (branch jump buffer), if AMD is likely not affected, due a different implementation. Or is it Variant 1 (if/else), which should slow down probably a lot of work cases dramatically. A pre sorted array is a likely usage case, where branch predicition improves performance.

Thanks

*Add here some finnish profanity...

Upvotes: 0

Views: 777

Answers (1)

Peter
Peter

Reputation: 2320

Seems like AMD has Indirect Branch Restricted Speculation (ibrs) now in usage, restriced but not turned off completely. 

AMD Defaults:
Due to the differences in underlying hardware implementation, AMD X86 systems are not vulnerable to variant #3. The correct default values will be set on AMD hardware based on dynamic checks during the boot sequence.

pti 0 ibrs 0 ibpb 2 -> fix variant #1 #2 if the microcode update is applied
pti 0 ibrs 2 ibpb 1 -> fix variant #1 #2 on older processors that can disable indirect branch prediction without microcode updates

https://access.redhat.com/articles/3311301

So the notice from SUSE isn't really correct.

Upvotes: 1

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