CODEWITHSUNDEEP
c++makefilecompilationdependencies
Valentin Montmirail
Valentin Montmirail

Reputation: 2640

Makefile compiling the good files without the dependencies

I have a problem with the dependencies in my Makefile. There is no problem with the compilation, it compiles perfectly the good *.cc and *.hh but unfortunately, it does not re-compile the dependencies, thus there is no update in the executable.

Here is my makefile: 

EXEC      ?= program

SRCS      = $(shell find -name *.cc)
DEP       = $(SRCS:.cc=.d)

OBJDIR    = objs
OBJS     = $(SRCS:./%.cc=$(OBJDIR)/%.o)

CXX       = g++
CFLAGS    = -std=c++14 $(addprefix "-I", $(shell find -type d))

## Clean rule
.PHONY: clean
clean:
    rm -rf $(OBJDIR)
    rm -f $(EXEC)

$(EXEC) : $(OBJS)
    @echo "Linking: $@"
    $(CXX) $(OBJS) -o $@

-include $(DEP)

$(OBJDIR)/%.o : ./%.cc ./%.hh
    @mkdir -p $(@D)
    @echo "Compiling: $<"
    @$(CXX) -c $(CFLAGS) -MT $@ -MMD -MP -o $@ $<

It is probably something related to the flag used by g++ but I do not manage to find the solution; Thanks in advance for the help that you can provide on this issue,

Upvotes: 0

Views: 103

Answers (1)

Maxim Egorushkin
Maxim Egorushkin

Reputation: 136515

If you do not specify the filename for the generated dependency files, it is going to be ${@:%.o=%.d} (compiler logic). I.e. your dependency files are in $(OBJDIR) and not in ./ where your makefile expects them to be.

Two alternative solutions:

  1. DEP := $(OBJS:%.o=%.d).
  2. @$(CXX) -c $(CFLAGS) -MT $@ -MMD -MP -MF $(<:%.cc=%.d) -o $@ $<

Upvotes: 2

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