CODEWITHSUNDEEP
interfacepackagesystem-verilog
Douglas Lane
Douglas Lane

Reputation: 1

packages declared inside system verilog interface

Is it possible to define a package inside of a SystemVerilog Interface?

example:

interface my_ifc();

    package a;
        logic reset;
        logic clk_usb;

    endpackage

    logic Rwn; 
    logic [7:0] Addr;


endinterface

Upvotes: 0

Views: 1023

Answers (2)

nick_g
nick_g

Reputation: 489

Package is a way to share code between modules, interfaces and programs in SystemVerilog. In your case, you could create a package outside the interface and then just import whatever you wish inside the package, in order to be made visible. Like this:

import a::*;

But the package, written inside the interface, is of no usefulness.

Upvotes: 0

dave_59
dave_59

Reputation: 42673

No. A package must be declared outside of any other nested scope (at the compilation unit level)

Upvotes: 1

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