Reputation: 6473
Sadly I'm forced to use and obscure microcontroller based on ARM Cortex-M1 core. I just found out that the latest CMSIS (5.2) does not support it and official CMSIS docs say this:
CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the ARMv8-M architecture including security extensions.
I guess Cortex-M1 is not very popular. But what should I do without CMSIS? My vendor ships support package which strangely enough includes CMSIS files for this core, namely, core_cm1.h; it's full of ARM copyrights and does not appear to be written directly by said vendor. File comment lists CMSIS version V3.20 from 25 February 2013. But I can't find it anywhere else, neither in higher versions of CMSIS nor in lower.
In "Definitive Guide to the ARM Cortex-M0" by Joseph Yiu I found this quote:
There is also a small chance that the software needs minor adjustment because of execution timing differences. At the time of writing, no CMSIS software package is available for the Cortex-M1. However, you can use the same CMSIS files for the Cortex-M0 on Cortex-M1 programming, because they are based on the same version of the ARMv6-M architecture.
I diffed core_cm0.h from CMSIS 4.0 and core_cm1.h from my vendor and found only very minor differences (like, 1 << smthn became 1u << smthn in a couple of places). Than I diffed core_cm0.h from CMSIS 5.0.2 and core_cm1.h from my vendor and found a lot of differences, structs are different, inline functions for NVIC are different and so on.
So my question is: is it really safe to use core_cm0 for Cortex-M1 even for latest CMSIS? Or should I play it safe and stick to my vendor's files (even though I have no idea where did it get them)?
Upvotes: 0
Views: 334
Reputation: 1789
Cortex-M1 is very similar to Cortex-M0 from a software point of view. At the CMSIS level, using core_cm0.h (latest CMSIS) will work fine.
You might also find compiler switches don't support Cortex-M1 - in this case treat it as if it were M0.
Upvotes: 0
Reputation: 11
You can use the Cortex-M0 CMSIS-CORE header on Cortex-M1. There are couple of things you need to be aware: - WFI, WFE and SEV instructions are not available in Cortex-M1. - Cortex-M1 has an auxiliary control register for I-TCM enable control. You need to declare that manually if you need to switch I-TCM enable. - CPU ID register has different value - Instruction execution timings are different - Interrupt latency is not constant.
There is a lot of code changes from CMSIS-CORE 4 to CMSIS-CORE 5. But those changes are focus on supporting of additional tools, general coding styles and for future extension of CMSIS. Hope this helps.
Upvotes: 1