CODEWITHSUNDEEP
verilogquartus
hanno
hanno

Reputation: 6513

Taking the top 64 bits from a multiplication in verilog

I have two 64 bit registers that I'd like to multiply together. I'm only interested in the top 64 bits of the result. What is the best way to write this in verilog? I tried

c = (a*b)[127:64]

which doesn't work. So right now I'm assigning the result of the multiplication to a 128 bit register, then only ever use the top 64 bits of that register. But it seems like a waste to have the lower 64 bits calculated and stored. Or is the synthesizer smart enough to never actually synthesize these bits if they are never used?

Upvotes: 0

Views: 1582

Answers (3)

Karan Shah
Karan Shah

Reputation: 1992

You can do something like this : 

typedef logic [127:0] QWORD;

c = (QWORD'(a*b)) >> 64;

Upvotes: 0

dave_59
dave_59

Reputation: 42698

If you can move to SystemVerilog, you can write

c = {a*b}[127:64];

SystemVerilog allows you to part-select a concatenation. But as others have mentioned, it won't save you that much hardware.

Upvotes: 2

Tushar
Tushar

Reputation: 499

wire c_tmp[127:0];
reg c[64:0];

assign c_tmp = a*b;
assign c = c_tmp[127:64];

The multiplication result will always be 128-bits. You can't save that cost. All you can save is the register cost. While making c_tmp as wire you are just using the wires not actual registers. And, you can choose to make c as 64-bit register.

Upvotes: 3

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