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JCLL
JCLL

Reputation: 5545

robustness of Xilinx ISE block ram inference

I have a question regarding the robustness of Xilinx ISE block ram inference.

I don't have xilinx ise installed on my machine (today) but I usually infer block rams perfectly using a dedicated coding, basically relying on :

type   ram_type is array(2**ADDR_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);

My question is : could you tell me if ISE will infer a correct block ram with

signed(DATA_WIDTH-1 downto 0)` instead of `std_logic_vector(DATA_WIDTH-1 downto 0)

or even more (in a package):

subtype signed8 is signed(7 downto 0)

and then

type   ram_type is array(2**ADDR_WIDTH-1 downto 0) of signed8;

I know the synthesizers are sometimes touchy...

Upvotes: 2

Views: 1168

Answers (3)

Saar Drimer
Saar Drimer

Reputation: 1191

This is a general comment, not specific to your problem. Trying to hypothetically second guess a synthesis tool isn't very productive. Results can vary with tool versions and the context of your design and implementation (different switches, optimization goals, target architecture, etc.) ISE/XST is free... download it and try your code. Then you could ask the question more meaningfully... "Why does XST version X.Y not infer a Block RAM under these conditions?" Then we can also discuss whether XST has the correct and expected behaviour or not.

Upvotes: 5

Erick Tejada
Erick Tejada

Reputation: 271

Besides the link Josh suggested (which goes in detail about RAM implementation by XST), here is another document at Xilinx's Website, which explains different RAM Implementations and their tradeoffs (page 76):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/sim.pdf

As a side note, I have used the "array" approach and worked great for small Block RAM sizes. But, I have to say that I tried using it to generate a Memory Module that was much larger than the size of 1 BlockRAM in my Spartan-6 and it couldn't infer it (XST tried to implement it as Distributed RAM). I solved the problem by directly instantiating the BlockRAM Macros Xilinx's provide and by creating the proper memory decoding modules to select/write/read to the appropriate individual BlockRAMs in the Memory Module.

Upvotes: 3

Josh
Josh

Reputation: 3655

I haven't tested this myself, but the "signed" type is derived from the std_logic type, so I don't see why this shouldn't work.

Assuming you are using XST for synthesis, the XST user guide is a good place to start to see what Xilinx officially states XST will recognize for block ram inference. XST User Guide for 12.4 (pdf)

Upvotes: 5

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