CODEWITHSUNDEEP
vhdl
Khalil Meftah
Khalil Meftah

Reputation: 73

Numeric operation in vhdl

i'm new in vhdl programming language. i'm trying to make a full adder with "+" operator , i made the code and l compiled as well but when i simulate it the output are very weird and doesn't mutch with the full adder outputs,i think that the error probably gonna be in the vector length, but i can't fix it.

    library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity adder is
port (a,b,c : in std_logic;
    s,d : out std_logic);
end entity;

architecture arc_adder of adder is
signal z : std_logic_vector (1 downto 0);
signal w : std_logic_vector (3 downto 0); 
begin 
z <= ('0'&a + ('0'&b));
w <= '0'&z + "00"&c;
s<=w(0);
d<=w(1);

end architecture;

Upvotes: 0

Views: 233

Answers (1)

Gautitho
Gautitho

Reputation: 623

You have to use unsigned to type with the "+" operator.

Unsigned type is included in ieee.numeric_std.all

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder is
port (a,b,c : in std_logic;
    s,d : out std_logic);
end entity;

architecture arc_adder of adder is
signal z : std_logic_vector (1 downto 0);
signal w : std_logic_vector (3 downto 0); 
begin 
z <= std_logic_vector(unsigned('0'&a) + unsigned('0'&b));
w <= std_logic_vector(unsigned('0'&z) + unsigned("00"&c));
s<=w(0);
d<=w(1);

end architecture;

Upvotes: 2

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