CODEWITHSUNDEEP
verilog
start01
start01

Reputation: 141

How do I make IO ports which by made of generate function in verilog?

I'm trying to make a simple DUT witch is including so many instances to implement to FPGA.

How do I make I/O ports which by made to instantiated DUT?

AS you can see the below code, there are TEST DUT, and I want to make 84 input_data I/O in TOP module.

If I use a way of using the below, top's input_data is connected to all of instances's input_data.

But I want to make each 84's I/O ports and connect them.

But I don't know how to do that.

Would you please help me what am I supposed to do ?

module top(

   input_data0,
   input_data1,
   input_data2,
   //...
   input_data83,

// TODO make I/O ports
);
// to declare reg/wire signals.

  input  signed [49:0] input_data0;
  input  signed [49:0] input_data1;
  input  signed [49:0] input_data2;
   //....
  input  signed [49:0] input_data83;


  // I'd like to connect between input_data0~input_data83 and u_test's 83 input_data 



genvar i;
generate

    for (i=0; i<84; i=i+1) begin : amp
    TEST u_test (
        .in_input       (   input_data  )
    );  
end 



endgenerate

endmodule

Upvotes: 0

Views: 1196

Answers (1)

dave_59
dave_59

Reputation: 42623

You can't do this in Verilog. In SystemVerilog, you would make your input_data port an array.

The best you can do in Verilog, is create a very big vector, and take a slice of it to connect to each TEST module

module top( input wire [(84*50)-1:0] input_data,

// TODO make I/O ports
);

genvar i;
for (i=0; i<84; i=i+1) begin : amp
    TEST u_test (
        .in_input       (   input_data[i*50 +:50] )
    );  
end 
endmodule

Upvotes: 1

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