CODEWITHSUNDEEP
system-verilog
Rocky Zheng
Rocky Zheng

Reputation: 31

how to define the input and output for the interface in systemverilog

Here I have a simple example below. 

module A(o,clk,rst,i);
  output o;
  input i,clk,rst;
  ...
endmodule

and here is an interface class definition below.

interface my_if(input bit clk);
  logic o,rst,i;
  wire clk;

  clocking cb@(posedge clk);
    input o;         // why input here ?
    output i,rst;    // why output here ?
  endclocking
  ...
endinterface

My question is how to decide the signal inside cb is input or output ??

Thank you !

Upvotes: 0

Views: 2301

Answers (1)

dave_59
dave_59

Reputation: 42616

There are many uses of input/output in SystemVerilog, which can be confusing.

For ports, they the flow of data across a boundary. For a clocking block, they represent whether a signal is passively being sampled, or actively driven. Depending on the situation, it is perfectly reasonable to have a port declared as an output, and the same signal declared as a clocking block input.

Upvotes: 2

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