CODEWITHSUNDEEP
chiselgtkwave
FabienM
FabienM

Reputation: 3741

How to change timescale in vcd generated by chisel3 iotester

I already asked a similar question for chisel2 in case of C++ backend. But now I'm using The template example with iotester (peek and poke) with chisel3.

With the following code (can be found on my github project page):

class TapTempoUnitTester(t: TapTempo) extends PeekPokeTester(t) {
  private val tptmp = t

  def pushbutton(button: Bool) {
   poke(button, 0)
   step(1)
   poke(button, 1)
   step(10)
   poke(button, 0)
  }

  val tclk = 10
  val tus = 1000/tclk
  val tms = 1000*tus
  val ts = 1000*tms

  //0
  pushbutton(tptmp.io.button)
  step(2*tms)
  //1
  pushbutton(tptmp.io.button)
  step(1*tms)
  //2
  pushbutton(tptmp.io.button)
  step(1*tms)
}

If I run the testbench with sbt following command :

sbt 'test:runMain taptempo.TapTempoMain --backend-name verilator'

It's launching the testbench and generate a VCD file that can be seen with gtkwave in following directory :

test_run_dir/taptempo.TapTempoMain962904038/TapTempo.vcd

But the timescale in this vcd file is :

$timescale 1ns $end

What is the right way to change this timescale (other than open vcd file an change it directly) ?

Upvotes: 1

Views: 487

Answers (1)

Jack Koenig
Jack Koenig

Reputation: 6065

I believe there is limited support for modifying VCS flags, but I don't think there is equivalent support for the Verilator backend. You could ask for such support on this issue: https://github.com/freechipsproject/chisel-testers/issues/148

Upvotes: 2

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