CODEWITHSUNDEEP
vhdlverilogxilinx
nichollsg
nichollsg

Reputation: 390

How to work with DDR in synthesizeable Verilog/VHDL?

I am working on implementing a DDR SDRAM controller for a class and am not allowed to use the Xilinx MIG core.

After thrashing with the design, I am currently working synchronously to my system clock at 100MHz and creating a divided signal "clock" (generated using a counter) that is sent out on the IO pins to DDR SDRAM. I have some logic that feeds me the "rising" edge strobes of this signal clock as I am aware that I cannot use a signal to clock a process. However, this divided clock method runs very slow and I have concerns that I am not meeting the minimum required frequency of the external DDR SDRAM. I am hoping to speed up my read/write bursts, but to do so, my spartan3e will struggle with anything higher than 100MHz. After looking around online, I found this code from EDA Board:

process(Input_Clk,Reset_Control)
begin
    if (Reset_Control = '1') then
        Output_Data     <= (others => '0');
    elsif  rising_edge(Input_Clk) then
        Output_Data     <= Input_Data1;
    elsif falling_edge(Input_Clk) then
        Output_Data     <= Input_Data2;
    end if;
end process ;

I have written a lot of VHDL, but have never seen something like this before. I'm sure this works fine in simulation, but it doesn't look synthesizable to me. The poster said this should be supported by 1076.6-2004. Does this infer two flip-flops, one clocked on the rising edge and one on the falling edge whose outputs both feed into a 2:1 mux? Does Xilinx support this? I want to avoid having to instantiate a DCM as crossing these clock domains will definitely slow me down and will add undesired complexity. Is there a way to safely generate my DDR data that is being sent to and received from DDR SDRAM without the Xilinx primitive for the MIG? How would I perform the receiving of DDR data in Verilog?

For reference, we have to code in Verilog, so I'm not too sure on how to translate that VHDL process to a Verilog always block if it is synthesizable. We are using the Micron MT46V32M16 if that is relevant.

Here are the timing diagrams for what I am trying to replicate:

burst read

burst write

Upvotes: 1

Views: 3990

Answers (1)

Oldfart
Oldfart

Reputation: 6259

I would say that implementing a DDR controller 'for class' is rather challenging. In the companies I worked for they where left for senior engineers to build.

First about the Verilog code shown:
Yes, you are right that can not be synthesized.

The approach to double-clocking inputs is to have two data paths. One on the rising edge and one on the falling edge. In a second stage the two are put in parallel but with double the data width. Thus a 32-bit wide DDR produces 64 data bits per 'system' clock.

More difficult is to clock the arriving data at the right time. As your read diagram shows the data arrives in the middle of the clock edge. For that you need a delayed clock. In an ASIC that is done using a 'tune-able' delay line which is calibrated at start-up and regularly checked for the phase. In an FPGA that would requires some esoteric logic.
I have not been close to DDRs chips for a while, but I think all the modern ones (DDR2 and up?), output a clock themselves to help with the read data.

Also after you have clocked the read data in, using that shifted clock, you have to get the data back to the system clock which requires an asynchronous FIFO.

I hope that gets you started.

Upvotes: 1

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