CODEWITHSUNDEEP
x86operating-systemvirtual-memory
Kay
Kay

Reputation: 797

How does an OS "deal in" virtual addresses and physical addresses

From what I understand from Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide, paging is enabled on a per-core basis: either off, or on.

As such, how does an OS "deal" in physical addresses? Most immediately, how would it manage the page table structures, and associated page frames?

Of the two things I can think of:

Upvotes: 3

Views: 1241

Answers (2)

Peter Cordes
Peter Cordes

Reputation: 366096

Most OSes map all of physical memory to a range of virtual addresses, with a kernel-only mapping. e.g. https://www.kernel.org/doc/Documentation/x86/x86_64/mm.txt is Linux's memory map.

Note the up-to-64TB "direct mapping" region. If you know a physical address, you access 0xffff880000000000 + phys_addr in kernel virtual address space.

Linux uses 1G hugepages for the direct mapping, so TLB misses are rare.

Things get complicated when there isn't enough virtual address space to easily map all physical RAM into part of virtual address space, like in 32-bit with more than 2GiB of RAM. Then the kernel has to treat part of physical RAM as "highmem" that can't be used directly for some things (e.g. for page tables).

Upvotes: 3

Hadi Brais
Hadi Brais

Reputation: 23739

paging is enabled on a per-core basis: either off, or on.

Yes, each core has its own set of control registers.

The OS would, during startup, and before enabling paging, map a section of linear addresses directly to physical addresses.

Typically, an OS would enable paging during startup. Before it does that, it first creates a multi-level page table. There must be at least one virtual-to-physical page mapping so that when paging is enabled, at least there would be one page that can be accessed without triggering a page fault. The OS then stores the physical base address of the first-level page table (page directory) in the CR3 control register. Finally, to actually enable paging, the OS sets CR0[PG] to 1. When an instruction changes CR0[PG] from 0 to 1, all subsequent instructions effectively start using the paging unit (with one exception, see below). This means all effective addresses generated by the address generation unit of the core and mapped to the corresponding linear addresses by the segmentation unit (if applicable) are intercepted by the paging unit to be mapped to physical addresses using the page tables. The key point here is that CR3 contains a physical address, not a logical or a linear address, which breaks what would otherwise be an infinite cycle of address translation.

This means that the data structures used by the OS and its code must also be mapped to virtual pages. Typically, the virtual address space of each process is partitioned into a user-mode part and a kernel-mode part. The kernel partition of the virtual address space of each process is mapped to the same physical pages. For this reason, no matter which process calls into the kernel, the kernel can use the same virtual addresses and the same virtual address space of the calling process. The kernel pages are protected by setting a flag in the their page table entries.

The OS would actually disable paging to perform these types of tasks, then reenable it.

Technically, the OS can disable paging any time it wants. But that is not necessary. The page tables themselves are also mapped to virtual addresses so that the OS can maintain them without disabling paging. This is done by setting up one first-level page table entry in a special way called self-mapping or recursive mapping (the article includes nice figures that explain the concept very well).

However, paging might be disabled beyond the control of the OS. This happens when a system management mode interrupt (SMI) occurs, on which both paging and protected mode segmentation are disabled. The SMI handler (registered by the OS) runs in a special mode called the SM mode which is similar to real mode. Upon returning from the SM mode and if protected mode segmentation and paging were enabled before the SMI occurs, they will automatically be re-enabled.

Upvotes: 2

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