CODEWITHSUNDEEP
castingvhdlxilinx-ise
mark_infinite
mark_infinite

Reputation: 383

Connecting a STD_LOGIC to a one bit STD_LOGIC_VECTOR

I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard.

The problem is that it created a write enable signal (wea) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch:

Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector

How can I cast encnt, which is std_logic, to a one bit std_logic_vector?

(ISE doesn't allow me to change wea from the file of memory.)

Upvotes: 4

Views: 13138

Answers (1)

scary_jeff
scary_jeff

Reputation: 4374

This is a pretty common scenario with these IP blocks. You can easily associate your std_logic signal like this:

wea(0) => encnt,

Instead of associating wea as a whole, you are just associating that one element (0). As wea only has one element, this assigns the whole vector.

Upvotes: 6

Related Questions