Reputation: 3
I try to get compiler directive in a verilog parser which give me the true file name/path and the true current line in the non-preprocessed file.
Verilog language needs a preprocessing pass I have, but during the visit I have to know the current file name (which can't change by the `include directive) and so the true current line in the non-preprocessed file .
The preprocessing part add the verilog directive `line which indicates the current file and line. Then I send the preprocessed buffer to the antlr Lexer, parse and extract all verilog information with a visitor. I have to keep the verilog compiler `line directive in the verilog grammar description:
Preprocessing_line
: '`line ' Decimal_number String Decimal_number '\n' -> channel(2)
;
Now, I don't know how to get this dedicated channel information at any point in the visitor? The target language for this parser is Python3.
Upvotes: 0
Views: 211
Reputation: 6001
Given that the Preprocessing_line
tokens may not have a reliable relation to the parse-tree tokens (different Verilog compilers can be a bit loose about where they inject the reference lines), the easiest solution is to create a temporary index prior to the visitor walk.
That is, after parsing the pre-processed Verilog source, do a quick pass over the entire token stream (BufferedTokenStream#getTokens
), picking out the Preprocessing_line
tokens, and building a current_line -> original_line
index.
Then, in any visited context, examine the underlying token(s) (ParserRuleContext#getStart
, #getStop
, #getSourceInterval
) to find their current_line
(Token#getLine
)
Upvotes: 1