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I recently read the GK110 white paper, which claims that each SM has 4 warp schedulers, and each with dual Instruction Dispatch Units. On each cycle, each warp scheduler selects an eligible warp to execute instructions for it.
My question is in GK110, each SM contains 192 CUDA cores (SP), but SM can only schedule 4 warps on each cycle, that is 4 x 32 = 128 cores will be used (assume all threads only need single-precision unit), then what will the other 64 cores do?
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