CODEWITHSUNDEEP
system-verilog
Rocky Zheng
Rocky Zheng

Reputation: 31

How to handle the interface with package in systemverilog

I am creating a simple uvm tb these days and I meet an issue with interface usage. Here is my code.

in the /my_proj/tb_uvm/intf/my_if.svh file: (interface definition)

interface my_if (
    input iCLK,
    input iRSTb,
    inout data
);
clocking monitor_cb @(posedge iCLK);
    input iRSTb;
    input data;
endclocking
modport monitor_mp(
    clocking monitor_cb
); 
endinterface : my_if

and I need to instance this interface in the /my_proj/tb_uvm/agent/my_driver.svh file :

class my_driver extends uvm_driver;
    `uvm_component_utils(my_driver)
    virtual my_if m_vif;
    ...
endclass

I tried to define a package file(named my_agt_pkg.sv) under /my_proj/tb_uvm/agent/ because there are several driver/monitor files in this directory including the my_driver.svh I mentioned above. 

package my_agt_pkg;
    import uvm_pkg::*;

    `include "my_driver.svh"
    `include "../intf/my_if.svh"
     ....
endpackage

but I failed to compile because of below error. Could anyone kindly give me a help on this issue ?

Found 'interface' inside package before 'endpackage'. 'interface' inside 'package' is not allowed.

Upvotes: 0

Views: 5564

Answers (1)

dave_59
dave_59

Reputation: 42748

The error message means what is says: you are not allowed to declare an interface inside a package.

A virtual interface is a peculiar concept. It behaves like a class variable, but an interface gets defined and instantiated like a module.

Just move your interface declaration outside the package

Upvotes: 3

Related Questions