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c++stm32i2c
Kuba
Kuba

Reputation: 63

how to calculate i2c timing for stm32l0

I got a stm32l0 series procesor and i dont know how to calculate i2c timing. I want to work with Bosh bme680/bme280 sensor. I find only Timming configuration tool for stm32F0/f3. Some1 know how to calculate it?

Upvotes: 1

Views: 9471

Answers (1)

pan-mroku
pan-mroku

Reputation: 891

TLDR: RM0377 Reference manual "Ultra-low-power STM32L0x1 advanced Arm®-based 32-bit MCUs", page 614 contains examples.

Note: I haven't actually worked with I2C yet. All the following is based on documentation.

  1. UM1749 User Manual "Description of STM32L0 HAL and Low Layer drivers" (p. 233):

    uint32_t I2C_InitTypeDef::Timing Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual

  2. RM0377 Reference manual "Ultra-low-power STM32L0x1 advanced Arm®-based 32-bit MCUs" (p.641):

    Timing register (I2C_TIMINGR)

    (...)

    PRESC[3:0] : Timing prescaler

    This field is used to prescale I2CCLK in order to generate the clock period t_PRESC used for data setup and hold counters (refer to I2C timings on page 587 ) and for SCL high and low level counters (refer to I2C master initialization on page 602 ).

    t_PRESC = (PRESC+1) x t_I2CCLK

    SCLDEL[3:0] : Data setup time This field is used to generate a delay t_SCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t_SCLDEL.

    t_SCLDEL = (SCLDEL+1) x t_PRESC

    Note: t_SCLDEL is used to generate t_SU:DAT timing.

    SDADEL[3:0] : Data hold time This field is used to generate the delay t_SDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during t_SDADEL.

    t_SDADEL = SDADEL x t_PRESC

    Note: SDADEL is used to generate t_HD:DAT timing.

    SCLH[7:0] : SCL high period (master mode) This field is used to generate the SCL high period in master mode.

    t_SCLH = (SCLH+1) x t_PRESC

    Note: SCLH is also used to generate t_SU:STO and t_HD:STA timing.

    SCLL[7:0] : SCL low period (master mode) This field is used to generate the SCL low period in master mode.

    t_SCLL = (SCLL+1) x t_PRESC

    Note: SCLL is also used to generate t_BUF and t_SU:STA timings.

    More info about prescalers can be found in paragraphs about timers (p. 433).

  3. RM0377 (p. 581):

    The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to 1MHz) I2C bus.

    So in order to communicate the I2C clock needs to be have appropriate frequency.

  4. RM0377 (p. 583):

    This independent clock source can be selected from the following three clock sources:

    • PCLK1: APB1 clock (default value)
    • HSI16: internal 16 MHz RC oscillator
    • SYSCLK: system clock Refer to Section 7: Reset and clock control (RCC) for more details.

  5. RM0377 (p. 604): I2C-SMBUS specification clock timings

  6. RM0377 (p. 602):

    t_SCL = t_SYNC1 + t_SYNC2 + {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x t_I2CCLK}

    The duration of t_SYNC1 depends on these parameters:

    • SCL falling slope
    • When enabled, input delay induced by the analog filter.
    • When enabled, input delay induced by the digital filter: DNF x t_I2CCLK
    • Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)

    The duration of t_SYNC2 depends on these parameters:

    • SCL rising slope
    • When enabled, input delay induced by the analog filter.
    • When enabled, input delay induced by the digital filter: DNF x t_I2CCLK
    • Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)

  7. BME280 Datasheet (p. 30):

    All modes (standard, fast, high speed) are supported.

Gathering it all up: Basing on the I2C clock frequency, and the speed you want to use, you need to choose such values of PRESC, SCLDEL, SDADEL, SCLH, SCLL that you comply to the I2C-SMBUS specification clock timings using formula t_SCL = t_SYNC1 + t_SYNC2 + {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x t_I2CCLK}

There are also some I2C_TIMINGR register configuration examples in RM0377 at page 614.

Upvotes: 5

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