CODEWITHSUNDEEP
vhdl
George Nemoukos
George Nemoukos

Reputation: 17

VHDL Error 10568 can't write to interface object "a" of mode IN

architecture behavioral of farc4bit is

component fa1bit
port( a, b, ci       : in  STD_LOGIC;
      s, co          : out STD_LOGIC );
end component;

signal c1,c2,c3: STD_LOGIC;

begin
a<=SW(7 DOWNTO 4);
LEDR (7 DOWNTO 4) <=a;

b<=SW(3 DOWNTO 0);
LEDR(3 DOWNTO 0) <= b;

ci<=SW(8);
LEDR(8)<=ci;

LEDG(3 DOWNTO 0)<=s;
LEDG(4)<=co;


FA1: fa1bit port map( A(0), B(0), ci, S(0), c1);
FA2: fa1bit port map( A(1), B(1), c1, S(1), c2);
FA3: fa1bit port map( A(2), B(2), c2, S(2), c3);
FA4: fa1bit port map( A(3), B(3), c3, S(3), co);

end Behavioral;

I can't understand why this is happening in my code and I can't find an answer please help me.I don't know what to do :(

Upvotes: 1

Views: 4209

Answers (1)

Oldfart
Oldfart

Reputation: 6269

The error message is rather comprehensive: You can't write to an signal which comes into a module.

a,b, and cin are all coming in a, b, ci : in STD_LOGIC; But you try to write them.

Upvotes: 3

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