CODEWITHSUNDEEP
riscv
ARK91
ARK91

Reputation: 373

Custom Instruction in RISCV

I am following the gem5 to add the custom instruction. My question is how to the interpret operands mentioned in "const struct riscv_opcode riscv_opcodes[]" in riscv-opc.h. For an example : {"mod", "I", "d,s,t", MATCH_MOD, MASK_MOD, match_opcode, 0 } .how "d,s,t" are interpret here? Can anyone explain the this whole statement

refLink :https://nitish2112.github.io/post/adding-instruction-riscv/

Upvotes: 1

Views: 1351

Answers (2)

Tawfiq Abuaita
Tawfiq Abuaita

Reputation: 107

This question is almost 4 years old, but since I spent a lot of time figuring out similar things, I would like to post my knowledge in case anyone needs it.

"mod" is the instruction label, "I" is the type of the instruction and in this case, it is an integer instruction. It takes three registers, the destination "d" register and the source registers "s" and "t".

The MASK_MOD and MATCH_MOD are used for the instruction matching in the assembler. The instruction matching is done by the function match_opcode that you are passing in the next parameter. This function does the instruction matching is done as follows:

((insn ^ MATCH_MOD) & MASK_MOD) == 0

This means that the instruction (32 bits in length) is XOR'ed with the MATCH_MOD and then the result is AND'ed with the MASK_MOD. The result must always be zero to match the "mod" instruction that you are adding. This means you have to define the instruction opcode, FUNCT7, and FUNCT3 accordingly in the riscv-opcodes/opcodes file included in RISCV-GNU-Toolchain. You should also define the MASK_MOD and MATCH_MOD in riscv-isa-sim/riscv/encoding.h.

Upvotes: 0

Pierre G.
Pierre G.

Reputation: 4431

According to the comment at the top of the array describing the instructions : /* name, isa, operands, match, mask, match_func, pinfo. */

The line says that {"mod", "I", "d,s,t",

mod belongs to the Integer ISA and that it is a triadic instruction, meaning that it takes 3 registers whose symbolic names are d,s,t. d being the destination register, s and t being source registers.

Upvotes: 1

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