CODEWITHSUNDEEP
verilogsystem-verilogassign
ptrck
ptrck

Reputation: 79

Bidirectional assignment in Systemverilog

I need to create mux block that works with inout pins. My module has n inputs and n outputs, I want to be able to switch between different outputs.

The problem that I am currently having is that I need to do that with inout pins. So if my output pin is pulled down, the input pin of the mux shall see that. This doesn't work with a common assign statement since it will only write in one direction. I have tried an alias statement, which works like a bidirectional assign, but I can not combine this with an if statement for the mux.

What I want to do:

alias net_out = (config) ? net1 : net2;

I have created an example on edaplayground

Thanks in advance, Patrick

Upvotes: 0

Views: 3706

Answers (1)

dave_59
dave_59

Reputation: 42616

You can use the bidirectional tran primitives, which is exactly how one would implement this in MOS hardware.

tranif1(net_out, net1, config);
tranif0(net_out, net2, config);

If you are looking to do this in hardware, this has to be something your technology supports. Most FPGAs would not support this.

However, if this config signal was a parameter and not a variable, you could use the alias statement with a generate-if

if(config)
  alias net_out = net1;
else
  alias net_out = net2;

Upvotes: 2

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