Reputation: 15
I am new to Verilog (and, to a lesser extent, programming) and am trying to create a program that finds the absolute value of a set of numbers and then calculates for a running average. The running average is 5 points wide, and goes across a data set that is about 40 numbers wide.
I am having trouble with the running average (lines 14-17 design, 24-28 test-bench) and am receiving the errors "o2/out is not a valid l-value in tb.avg." and "o2/out is declared here as a wire". How should I fix this?
Here is my design:
module absolute_value(i1,o1);
input signed [11:0] i1;
output signed [11:0] o1;
assign o1 = i1[11] ? -i1 : i1;
endmodule
module moving_average(k1,k2,k3,k3,k4,o2,out);
input k1, k2, k3, k4, k5;
output [11:0] o2;
output [11:0] out;
integer t;
always begin
assign o2 = (k1 + k2 + k3 + k4 + k5) / 5;
assign out = o2;
end
endmodule
And here is my test-bench:
module tb;
reg signed [11:0] i1;
wire signed [11:0] o1;
reg k1;
reg k2;
reg k3;
reg k4;
reg k5;
wire [11:0] o2;
wire [11:0] out;
absolute_value abs(i1,o1);
moving_average avg(k1,k2,k3,k4,k5,o2,out);
integer t;
initial begin
for (t = -10; t < 30; t = t + 1) begin
#1
i1 <= t;
$display("i1 = %d, o1 = %d", i1, o1);
assign k5 = k4 ? k4 : o1;
assign k4 = k3 ? k3 : o1;
assign k3 = k2 ? k2 : o1;
assign k2 = k1 ? k1 : o1;
assign k1 = o1;
$display("out = %d", out);
$moniter($time, "i1 = %d, o1 = %d, o2 = %d, out = %d k1 = %d, k2 = %d, k3 = %d, k4 = %d, k5 = %d", i1, o1, o2, out, k1, k2, k3, k4, k5);
end
end
endmodule
I'd bet that there are other errors in my program too, so any help is much appreciated.
Upvotes: 1
Views: 4624
Reputation: 6259
As mentioned in the comments:
Remove the always
and keep the output [11:0] out
or
Change to:
reg [11:0] o2;
reg [11:0] out;
always @( * )
begin
o2 = (k1 + k2 + k3 + k4 + k5) / 5;
out = o2;
end
Second error: Your port uses k1, k2, k3, k3, k4 and is missing k5.
Thirdly: please don't use the port style from last century. I advise you to switch to the new format:
module moving_average(
input k1, k2, k3, k4, k5,
output signed [11:0] o2,out
);
Or for the second case: output signed reg [11:0] o2,out
Fourth: it is $monitor
, not $moniter
Upvotes: 2