CODEWITHSUNDEEP
vhdlverilog
Ishu Gupta
Ishu Gupta

Reputation: 55

What happens if for loop variable in VHDL or verilog code is variable?

What issue occurs in simulation or synthesis if I assign a non-constant value to initial value of for loop variable in VHDL or Verilog? E.g- If I write a test case like:

module dut(input clk, d, output reg [5:0] q);
 integer i, j, k, l;
always @(posedge clk)
 begin
for(i =k;j < 4;k++, l++) begin
q[i] <= d;
end
end
 endmodule

What will be the issue?

Upvotes: 0

Views: 643

Answers (2)

dave_59
dave_59

Reputation: 42698

A for can be written as a do-while loop

for(<Initialization>;<Condition>;<Iteration>) <Statement>;

<Initialization>;
do
 begin
 <Statement>;
 <Iteration>;
end
while (<Condition>);

So once the clause i=kexecutes, it does not matter what happens to the value of k.

Synthesis requires that the total number of loop iterations be computed at compile time. You have to provide expressions that can be evaluated at compile time. So most likely if the starting and ending iteration values are not constants, the loop will not be synthesizable.

Upvotes: 1

Oldfart
Oldfart

Reputation: 6259

What will be the issue?

The issue is that you can only use the code in simulation. That is: you will not be able to synthesize the code and produce hardware from it.

In synthesis the for-loop is unrolled and hardware is generated for each step through the loop. For that the synthesis tool must know during compile time how often the loop is executed.

Upvotes: 2

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