CODEWITHSUNDEEP
system-verilog
imulsion
imulsion

Reputation: 9040

SystemVerilog ignore unused ports

I have a module that is instantiated many times in other modules. Two of the inputs to this module are used very rarely, and to avoid code bloat I don't want to have to connect them in every instantiation. Is there a way to mark these two ports to the compiler to indicate they can be left unconnected?

eg.

module mymod(input logic foo, unused1, unused2, output logic out);
//...
endmodule


module top(...);
//...
mymod(.foo(1'b0));
endmodule

will not compile due to port mismatch errors. How can I change the code so unused1 and unused2 don't need to be connected?

Upvotes: 1

Views: 3614

Answers (1)

dave_59
dave_59

Reputation: 42616

Yes, you can specify a default value for a unconnected port (See 23.2.2.4 Default port values in the 1800-2017 LRM)

module mymod(input logic foo, unused1='0, unused2='0, output logic out);
//...
endmodule

Another option is to explicitly leave these ports unconnected when instantiating. 

mymod(.foo(1'b0), .unused1(), .unused2() );

But in either case, your tool may have specific requirements with unconnected ports that you will have to deal with as they ask you to do.

Upvotes: 2

Related Questions