CODEWITHSUNDEEP
verilog
Yashas Lr
Yashas Lr

Reputation: 3

Calling Arrays in Verilog Structural Description

I am trying to pass only partial arrays from one verilog module to another and encounter an error every time i modify the code.

The code is as follows:

module 1:

module Koge_4(A,B,Cin,S,Cout);
input [3:0] A,B;
input Cin;
output [3:0]S;
output Cout;

Module 2: 

module Koge_64(A,B,Cin,S,Cout);
input [63:0]A,B;
input Cin;
output [63:0]S;
output Cout;
wire [15:0]c;
Koge_4 K1  ([3:0]A,[3:0]B,Cin,[3;0]S,c[0]); // sample structural code

I am basically trying to call the 4 bit (module 1) for every 4 bit of the input vector in module 2. Hence calling it 16 times for 64 bits.

Upvotes: 0

Views: 237

Answers (1)

Serge
Serge

Reputation: 12354

You are missing endmodule in the example and have complete mess with verilog syntax (see toolic's comment). Please read a Verilog tutorial.

Here is a cleaned up version of your code which you can compile. 

module Koge_4(A,B,Cin,S,Cout);
   input [3:0] A,B;
   input Cin;
   output [3:0]S;
   output Cout;
endmodule

module Koge_64(A,B,Cin,S,Cout);
   input [63:0]A,B;
   input Cin;
   output [63:0]S;
   output Cout;

   wire [15:0]c;

   Koge_4 K1  (A[3:0], B[3:0], Cin, S[3:0], c[0]); // sample structural code
endmodule // Koge_64

Upvotes: 1

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