CODEWITHSUNDEEP
vhdlmultiplication
MPA95
MPA95

Reputation: 185

VHDL multiplication for std_logic_vector

When simulating, I get a run time error, so I'm trying to run a RTL analysis in Vivado to see if the schematic of the component can be created at least. My code is the following:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity multiplicator_test is
    generic(
            WORD_SIZE: natural := 8;
            EXP_SIZE: natural := 3
        );
        port(
            input_1: in std_logic_vector(WORD_SIZE-1 downto 0);
            input_2: in std_logic_vector(WORD_SIZE-1 downto 0);
            result: out std_logic_vector(WORD_SIZE-1 downto 0)
        );
end entity multiplicator_test;

architecture multiplicator_test_arch of multiplicator_test is
    constant SIGNIFICAND_SIZE: natural := WORD_SIZE - EXP_SIZE - 1;

    signal significand: std_logic_vector(SIGNIFICAND_SIZE-1 downto 0) := (others => '0');
    signal exponent: std_logic_vector(EXP_SIZE-1 downto 0) := (others => '0');
    signal sign: std_logic := '0';
    signal aux: std_logic_vector((2*SIGNIFICAND_SIZE)-1 downto 0) := (others => '0');
begin
        aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));
        significand <= aux(SIGNIFICAND_SIZE - 1 downto 0);
        exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));
        sign <= input_1(WORD_SIZE-1) or input_2(WORD_SIZE-1);
        result <= sign & exponent & significand;
end architecture multiplicator_test_arch;

When running the analysis, I get:

ERROR: [Synth 8-690] width mismatch in assignment; target has 3 bits, source has 4 bits [(...)/multiplicador.vhd:27]

The line with the error is 27: 

aux <= std_logic_vector(signed(input_1(SIGNIFICAND_SIZE-1 downto 0))*signed(input_2(SIGNIFICAND_SIZE - 1 downto 0)));

Apparently the target (aux) is 3 bits, but really it should be 8.

Upvotes: 1

Views: 4001

Answers (1)

Layne B
Layne B

Reputation: 696

The line you've posted is not line 27, line 27 is the following:

exponent <= std_logic_vector(unsigned(input_1(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2))+unsigned(input_2(WORD_SIZE-2 downto WORD_SIZE-EXP_SIZE-2)));

As you can see, exponent only has 3 bits:

Exponent

The unsigned addition will need an additional bit for carry-out. Basically, there's an issue that you might overflow on the multiplication.

One way to solve this is to make your result and exponent one bit wider:

result: out std_logic_vector(WORD_SIZE downto 0)
signal exponent: std_logic_vector(EXP_SIZE downto 0) := (others => '0');

Yields: Schematic

Upvotes: 4

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