CODEWITHSUNDEEP
verilog
kevin1494
kevin1494

Reputation: 158

What happens if we use async reset block with sync reset?

Consider that I have a common verilog module that I want to be exported to 2 different kinds of designs - one on sync reset and the other on async reset.

What would be the right way to code an always block within this common module so that it works fine in both kinds of designs? I am thinking we can use the async reset block like this - 

always @(posedge clk or negedge reset_) begin
  if(!reset_) temp <= 'd0;
  else <do something>
end

If i use sync reset then in async reset designs i have a problem if clocks start much later than reset assertion-deassertion so the required reset can be completely missed.

In sync reset we know the posedge of clk and negedge of reset_ will coincide always, so is there any issue with that?

Upvotes: 0

Views: 827

Answers (1)

Matthew
Matthew

Reputation: 13937

You could do this:

always @(posedge clk or negedge async_reset) begin
  if(!async_reset) 
    temp <= 'd0;
  else 
    if (!sync_reset)
      temp <= 'd0;
    else
      <do something> 
end

and then tie one or the other reset to INACTIVE (1'b1 in this case). If you're synthesising to an FPGA, I would imagine it would cost you nothing in area or speed. If you're synthesising to an IC, then I'd check what the synthesiser does with it.

Upvotes: 2

Related Questions