CODEWITHSUNDEEP
armarm64mmupage-tables
Milan
Milan

Reputation: 1529

MMU: Long descriptor page table sizes in AARCH64

I Would like to understand, memory covered at each level by page tables in AARCH64 with 4k granularity.

With 47 bit of VA, One could have level 0 to level 3.

At level 0 there could be one table which describes 512 Level 1 Page tables, Now each level 1 page table can describes 512 Level 2 page tables and further each level 2 page table can describes 512 Level 3 page tables.

So at level 3 there are 512 page tables of size 4k each and memory covered is 512*4k = 2MB , this is what only one page table of level 2 can cover and if we have 512 such level page tables at level 2 then total memory covered is 512*2MB = 1GB, right ?

Similar way, each table at level 1 points to 512 level 2 page tables( where each level 2 page tale covers 2MB).

So, 512*2MB= 1GB and if we have 512 level 1 page table and total memory covered is 512 GB , right ?

Similar way , Total memory covered at level 0 is 1024 GB, right ?

Upvotes: 0

Views: 768

Answers (1)

Siguza
Siguza

Reputation: 23820

You seem to have mixed up single page table entries with entire page tables at one point, lost one level somehow and added a bit rather than subtracted it.

Single page: 4'096
Level 3 table: 4096*512 = 2'097'152 = 2MB
Level 2 table: 4096*512*512 = 1'073'741'824 = 1GB
Level 1 table: 4096*512*512*512 = 549'755'813'888 = 512GB
Level 0 table: 4096*512*512*512*512 = 281'474'976'710'656 = 256TB

Note though that the above applies to a 48-bit address. That is, from the address 12 bits are used for the page offset, and 4 times 9 bits each as page table index (12 + 4*9 = 48).
For 47 bits, you simply only have 256 entries in the level 0 table, so you end up with 128TB of addressable memory.

Upvotes: 4

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