CODEWITHSUNDEEP
verilog
Tey'
Tey'

Reputation: 990

Declare vector ports without specifying their size in Verilog

When declaring a module in Verilog (2001?), is it possible to tell that some ports are vectors without indicating their size? The goal here is to handle vector ports of any size, without having to specify the sizes through parameters.

I know I can write something like what follows in Verilog, but I'd like to know if there's a way to get rid of the extra WIDTH_DATA parameter:

module my_module
#(
  parameter  WIDTH_DATA = 48
)
(
  input  Clk, En,
  input  [WIDTH_DATA-1:0] Data_in,
  output Ready,
  output reg [WIDTH_DATA-1:0] Data_out
);

This is possible in VHDL, using a declaration like that:

entity my_module is
  port (
    Clk      : in std_ulogic;
    En       : in std_ulogic;
    Data_in  : in std_ulogic_vector;
    Ready    : out std_ulogic;
    Data_out : out std_ulogic_vector
  );
end entity;

The module implementation can then know the size of Data_in at compile time using Data_in'length (same for Data_out).

Upvotes: 0

Views: 873

Answers (1)

dave_59
dave_59

Reputation: 42616

This is not possible in Verilog.

You can do something close to what you want in SystemVerilog using the interface construct. You can parameterize an interface, and connect that interface (or set of interfaces) to my_module.

interface my_intf #(int WIDTH);
  logic [WIDTH-1:0] data;
endinterface
module my_module(input clk, en,
                 my_intf in, out,
                 output ready);
  // $bits(in.data) - gives you the WIDTH
  // typedef type(out.data)  out_type // local typedef 
endmodule
module top;
  my_intf #(8) I1;
  my_intf #(16) I2;
  bit clk, en, ready;
  my_module M1 (.clk,.en, .in(I1), .out(I2), .ready);
endmodule

Upvotes: 1

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