CODEWITHSUNDEEP
verilogsystem-veriloghdl
TheSprintingEngineer
TheSprintingEngineer

Reputation: 319

Verilog always block with no sensitivity list

would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*)? Eg code:

always begin
if (sig_a)begin
 @(posedge sig_b); // wait for a sig_b posedge event
 @(negedge sig_b); // then wait for a sig_b negedge event
 event_true=1;  
end

if (event_true)begin
  @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true
  yes =1;
 end
 else yes =0;

end

Upvotes: 0

Views: 3330

Answers (2)

ondra
ondra

Reputation: 1

I tried it in Quartus, and both of these do result in the same realization after synthesis.

always x = counter[0] + counter[1];

assign y = counter[0] + counter[1];

I do not know how prevalent the support for this is.

Upvotes: -1

dave_59
dave_59

Reputation: 42658

Synthesis tools require a specific template coding style to synthesize your code. Most only allow a single explicit event control ar the beginning of an always block. Some of the higher-level synthesis tools that do allow multiple event controls only allow multiple occurrences of the same clock edge.

Simulation tools don't have these restrictions and will try to execute whatever legal syntax you can compile. BTW, your @((sig_c==1)&&(sig_a==0)) means wait for the expression to change value, not wait for it to become true. The wait(expr)construct means wait for the expression to become true.

Upvotes: 3

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