CODEWITHSUNDEEP
makefilegnu-make
jap jap
jap jap

Reputation: 342

Makefile: variables are not included from other makefile

I want to use a common.mk file for common variable definitions and include this file in other Makefiles but in the first example I've done it is not working so I think that I have misunderstood something.

This is the Makefile:

CC=gcc
CFLAGS=-g -Wall
LIB_FLAGS=-L/usr/local/lib/ -lcgreen

BUILDDIR=$(CURDIR)/build
SRC=$(wildcard *.c)

export BUILDDIR 
export CFLAGS
export LIB_FLAGS

#include common.mk  # HERE I INCLUDE THE common.mk where OBJ is defined

unittests: dir externals $(OBJ)
    @echo "SRC: $(SRC)"
    @echo "OBJ: $(OBJ)" # THIS PRINTS OBJ AS EMPTY <------------------------------
    $(CC) $(BUILDDIR)/*.o $(LIB_FLAGS) -o $(BUILDDIR)/unittests
    $(BUILDDIR)/unittests

externals:
    @$(MAKE) -C lib1 -f lib1.mk

dir:
    mkdir -p $(BUILDDIR)

This is the common.mk file:

 OBJ=$(patsubst %.c, $(BUILDDIR)/%.o, $(notdir $(SRC)))

$(BUILDDIR)/%.o: %.c
    @echo "File: "$<
    $(CC) -c $(CFLAGS) $< -o $@

clean:
    rm -f $(OBJ)

So I was expecting that the OBJ variable in the main Makefile had a object files list but it is empty and I don't understand why. Isn't it including the common.mk file the same as copying it's content into the Makefile?

Thanks

Upvotes: 0

Views: 410

Answers (1)

jap jap
jap jap

Reputation: 342

As @melpomene pointed out I was including the file like it is done in C and therefore commenting it out!

Sorry for wasting your time..

Upvotes: 0

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