CODEWITHSUNDEEP
verilogverilator
FabienM
FabienM

Reputation: 3751

How to tell verilator linter to not verify submodule?

I'm using verilator for linting my design with this commands :

verilator -lint-only -Wall top_design.v

But some submodule are not available (mainly because it template from FPGA constructor). Then I have these kind of errors :

%Error: efb.v:39: Cannot find file containing module: VHI
%Error: efb.v:41: Cannot find file containing module: BB
%Error: efb.v:43: Cannot find file containing module: BB
%Error: efb.v:45: Cannot find file containing module: VLO
%Error: efb.v:97: Cannot find file containing module: EFB
%Error: submod.v:163: Cannot find file containing module: OSCH

All submodules mentionned in these errors messages are templates for lattice machxo3 fpga.

Is there a solution to ask verilator to not care about these modules ?

Upvotes: 0

Views: 1129

Answers (1)

FabienM
FabienM

Reputation: 3751

According to official verilator forum, the only way to do it is to make «null module».

Upvotes: 0

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