CODEWITHSUNDEEP
makefilegnu-make
Sergei Shumilin
Sergei Shumilin

Reputation: 431

Define target for recursive makefiles invocation

What I need: make LAUNCHMAKES target dependent on something in order to not invoke sub makefiles when no source file has been changed.

SUB MakeFile contains collecting of all .cpp files in the dir and stores them to the obj/. Then no src file changed it still invokes and engenders "Entering directory - Leaving directory". I need to get rid of it when there is no need. I've read about --no-print-directory but it's not the case.

The project's structure:

Project
|----project
|    |----dir1
|    |    |----src1.cpp
|    |    `----Makefile
|    |----dir2
|    |    |----src2.cpp
|    |    `----Makefile
     `----main.cpp
|----obj
|    |----src1.o
|    |----src2.o
|    `----main.o
|----MakeFile

The code:

release: LAUNCHMAKES obj/main.o
    $(CXX) $(CXXFLAGS) main.o src1.o src2.o -o result

LAUNCHMAKES: (?)
    for i in $(SUBDIRS); do \
    $(MAKE) -C $$i CXXFLAGS=$(CXXFLAGS);  \
    done

obj/main.o: project/main.cpp
    $(CXX) $(CXXFLAGS) -c $< -o $@

Upvotes: 0

Views: 244

Answers (1)

Renaud Pacalet
Renaud Pacalet

Reputation: 29050

Not a solution to your problem but an example of a non-recursive Makefile, just to show you how simple it could be for your simple example project:

SUBDIRS := dir1 dir2
OBJDIR  := obj
SRCS    := $(shell find . -type f -name '*.cpp')
OBJS    := $(patsubst %.cpp,$(OBJDIR)/%.o,$(notdir $(SRCS)))
VPATH   := $(SUBDIRS)

.PHONY: release clean

release: result

result: $(OBJS)
    $(CXX) $(LDFLAGS) $^ -o $@

$(OBJDIR)/%.o: %.cpp
    $(CXX) $(CXXFLAGS) -c $< -o $@

clean:
    rm -f $(OBJDIR)/*.o result

Demo:

$ make
g++  -c dir2/src2.cpp -o obj/src2.o
g++  -c dir1/src1.cpp -o obj/src1.o
g++  -c main.cpp -o obj/main.o
g++  obj/src2.o obj/src1.o obj/main.o -o result

Upvotes: 1

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