General Verilator question: When I specify a hierarchical Verilog design with multiple modules, split in several files, is the design then always flattened to a single c++ class or is there a possibility that Verilator retains the hierarchy by creating a class for each separate module ?

Reputation: 3194

Can Verilator create a class hierarchy?

General Verilator question:

When I specify a hierarchical Verilog design with multiple modules, split in several files, is the design then always flattened to a single c++ class or is there a possibility that Verilator retains the hierarchy by creating a class for each separate module ?

Upvotes: 1

Reputation: 3194

Adding // verilator public will generate seperate classes. There is also a SystemVerilog DPI-C that lets you access the internal wires via C.

Upvotes: 0