CODEWITHSUNDEEP
embeddedcan-bus
Günkut Ağabeyoğlu
Günkut Ağabeyoğlu

Reputation: 424

CAN Bus Bit Timing Calculation

I am kind of confused with CAN bus bit timing calculation so from the datasheet for 250 kbps and 8 MHz clock I have calculated these:

SJW=3, BRP=0, SEG1PH = 6, PRSEG=5, PHSEG2=4.

However when I use CAN Bus bit timing calculator program it gives these results:

SJW =1; BRP =2; PHSEG1 = 1; PHSEG2 = 2; PROPSEG = 4;

These are quite different results and it seems like both gives me around 50 kbps instead of 250 kbps. Are there any easy way to calculate these constraints? Or more understandable step by step calculation guide rather than that are on the internet or in datasheet which are quite complex and want you to decide some parameters by yourself such as SJW! Thanks.

Upvotes: 1

Views: 2251

Answers (2)

Aleks Yash
Aleks Yash

Reputation: 1

Thank you, so I fix the rates as: SJW=1, Seg1_PH=7, Seg2_Ph= 2, Prop_Seg= 6. Sample point will be fixed to %86.6

That's an example of an approach of following some rules without understanding the cause. The interval values picked above are of much more importance than the sample point requirement by itself, which in most cases is not as important at all. Your seg1 and seg2 values would better be roughly equal, prop_seg should correspond to bus length and their combination should meet the oscillator tolerances. The sample point could be in a range 65-90%, any of which by itself would be just fine.

Too late sample point makes it impossible for most MCUs to work from internal oscillator in case of emergency external quartz malfunction (clock security system makes it possible to switch MCU PLL to internal source in such cases on the fly) because the frequency tolerance gap becomes too tight (less than 1%) for usually rather inaccurate internal oscillator (1-2% under normal conditions). And the large propagation segment is really not needed in case of low speeds (50 kbps and below) or short buses (tens of meters at most) and with no gateways or galvanic isolators on the way.

Upvotes: 0

Lundin
Lundin

Reputation: 213832

I haven't used the PIC CAN controllers, but in general it goes something like this:

Phase seg 2 in relation to the total amount of tq gives the location of the sample point. No matter which CAN application you are using, I would advise to use the standard recommendations of CANopen, which is a sample point of 87.5%, with acceptable locations are between 85% - 90% (it's more lenient at the highest baudrates).

So 1 - tqPHSEG2 / tqtotal should be near 87.5%. In your case 1 - 4/15 = 0.73. You need to fix this by increasing the size of the other segments or lowering the size of phase seg 2. This is always a bit of trial & error.

As for baudrate, you probably get some formula along the lines of:

clock / (tqtotal * baudrate) = prescaler

Your specific CAN controller will give the exact formula for that particular hardware. Keep in mind what's the clock source, is it the raw oscillator, is it the system clock, is it something else? (PIC are notorious for using various system clock dividers and then you might have PLL adjustment on top of that.)

SJW doesn't affect the baudrate. It is the allowed re-sync width used for baudrate mismatches, mostly relevant at higher baudrates. At 250kbps, SJW=1 should work just fine.

Upvotes: 3

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