CODEWITHSUNDEEP
makefilecompilation
user10416282
user10416282

Reputation: 63

Defining path variable for a make file

In my assignment instructions, I was told to make a

Makefile without absolute directory names or derived binary files. Execution of make with no parameters should build the target program "wordpairs". Assume that the environment variable GET_WORD is defined as the pathname of a directory which contains directories "include" and "lib" containing getWord.h and libget.a

My directory for my code contains: pic

And my Makefile is:

#DIR := ${GET_WORD}
DIR := ${CURDIR}
Main : getWord.o crc64.o sTools.o hashingTools.o Main.c libget.a
    gcc -g -o wordpairs Main.c getWord.o crc64.o sTools.o hashingTools.o $(DIR)/lib/libget.a
getWord.o : getWord.c getWord.h
    cc -c $(DIR)/include/getWord.c $(DIR)/include/getWord.h 
#   cc -c getWord.c getWord.h 
crc64.o : crc64.c crc64.h
    cc -c  crc64.c crc64.h
sTools.o : sTools.c sTools.h
    cc -c  sTools.c sTools.h
hashingTools.o : hashingTools.c hashingTools.h
    cc -c  hashingTools.c hashingTools.h
clean :
    rm $(DIR)/include/*.h.gch

But when I run make, I get

make: *** No rule to make target 'getWord.c', needed by 'getWord.o'. Stop.

The files are in the folders include/lib.

I only understand the basic of make files, so can someone help me out how to achieve what I was assigned to do? What's causing this error?

(updated makefile code)

Upvotes: 0

Views: 3568

Answers (2)

user10416282
user10416282

Reputation: 63

So apparently I just need to define GET_WORD variable where the grade can change it to a specific location. The thing is that apparently you cant call variables in the requirement file line (see how I didnt specific anything for getWord.o)

GET_WORD = /home/tam#change this!
wordpairs : Main.c crc64.o hashingTools.o sTools.o getWord.o  
    gcc -o wordpairs $^ -I ${GET_WORD}/include ${GET_WORD}/lib/libget.a 
getWord.o :
    cc -c ${GET_WORD}/include/getWord.c ${GET_WORD}/include/getWord.h 
crc64.o : crc64.c crc64.h
    cc -c $^
hashingTools.o : hashingTools.c hashingTools.h
    cc -c $^
sTools.o : sTools.c sTools.h
    cc -c $^
clean :
    rm wordpairs crc64.o hashingTools.o sTools.o *.h.gch
    @echo $(GET_WORD) ${GET_WORD}

Upvotes: 1

tripleee
tripleee

Reputation: 189297

getWord.o : getWord.c getWord.h looks for these files in the current directory.

You should apparently use GET_WORD to define a couple of additional variables, not redefine it to something else than what's given explicitly in the assignment.

If you figure out how to set INC to the include/ directory, your rule for these files should look something like

getWord.o : $(INC)/getWord.c $(INC)/getWord.h
    cc -c $^

Notice how a dependency on a file in another directory must include the directory name; and how make won't actually look at how to make a new thing until the dependency resolution forces it to (and even then it doesn't know that a string in the command it runs is equal to one of the dependencies just because the strings are identical, let alone then when they are different, as in your attempt).

Notice also the use of $^ to say "the things in the dependencies". Generally, you want to avoid repeating information - if you change something, you don't want to change it in many places because it's easy to forget (see also DRY principle.)

... I don't think the professor wants the .c file in the include directory, actually, though; just the .h file would be my guess.

As a further aside, to have just make without arguments create a particular target, put it as the first target in your Makefile.

I hope this is sufficient to help you see how to solve your assigment!

Upvotes: 0

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