CODEWITHSUNDEEP
assemblysimdriscv
Gianluca Brilli
Gianluca Brilli

Reputation: 69

How to use vector operations in RISC-V Assembly

I am trying to exploit vector operations in RISC-V Assembly, in particular I need to compile my source code with arch RV64iV or RV64GV. I am using riscv64-unknown-elf- toolchain, with the following parameters:

riscv64-unknown-elf-gcc -o test -march=rv32iv test.s

but I get the following error:

Assembler messages: Fatal error: -march=rv32iv: unsupported ISA subset `v'

Thanks

Upvotes: 1

Views: 1858

Answers (2)

maxschlepzig
maxschlepzig

Reputation: 39195

As of early 2020, the RISC-V vector extension "V" specification is at version 0.8 and still has draft status.

However, there are "V" ports of the GNU gcc/binutils available and the Spike RISC-V simulator supports "V" 0.8, as well. The README of the "V" spec links to the relevant branches.

I recently published some notes on how to get started with RISC-V "V" 0.8 development, e.g. how to build the right toolchain, related components, assemble, compile "V" code and how to test it with Spike.

Upvotes: 1

Palmer Dabbelt
Palmer Dabbelt

Reputation: 1068

As of February 2019 there is no standard RISC-V vector extension, which means there is no support in standard RISC-V toolchains. There are various drafts of the vector extension floating around, but nothing supported by software.

Upvotes: 1

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