CODEWITHSUNDEEP
vhdl
Claudio La Rosa
Claudio La Rosa

Reputation: 161

How to create an asynchronous Edge Detector in VHDL?

I am new to VHDL. I would like to create an Edge Detector that works asynchronously (without use of clock signal).

I am using a simple schematic for this:

edge detector

In Quartus II (Altera/Intel) I have this code:

----
signal MyInput_Change : std_logic;
----
process (MyInput)   
begin

  MyInput_Change<= not(not (MyInput)) xor MyInput;  --edge detector
  if ( MyInput_Change = '1' ) then 
       --change state of FSM
  end if;

But this code doesn't work.

What am I doing wrong?

Upvotes: 1

Views: 3393

Answers (2)

Jim Lewis
Jim Lewis

Reputation: 3973

I have had good luck with the attribute syn_keep (alternately keep depending on your synthesis tool). 

signal A1, A2, A3, A4 : std_logic ;
attribute syn_keep : boolean ;
attribute synkeep of A1 : signal is true ;   
attribute synkeep of A2, A3, A4 : signal is true ;   -- should be able to group them, but if not do it as A1
. . . 

A1 <= not A ; 
A2 <= not A1 ; 
A3 <= not A2 ; 
A4 <= not A3 ; 

EdgePulse <= A xor A4 ;

This works for many things, but some synthesis tools - and even some place and route tools may be able to remove these.

Good Luck. Let us know how it goes.

Upvotes: 0

Paebbels
Paebbels

Reputation: 16211

Declare signals:

signal I    : std_logic;         -- input
signal I_d  : std_logic := '0';  -- input delayed by 1 cycle
signal I_re : std_logic;         -- rising edge
signal I_fe : std_logic;         -- falling edge
signal I_ch : std_logic;         -- changed

Delay input signal:

I_d <= I when rising_edge(Clock);

Rising edge detection:

I_re <= not I_d and I;  -- old = 0, new = 1 => rising edge

Falling edge detection:

I_fe <= I_d and not I;  -- old = 1, new = 0 => falling edge

Edge / change detection:

I_ch <= I_d xor I;      -- old <> new       => changed

Upvotes: 2

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