CODEWITHSUNDEEP
verilogsystem-verilogformal-verificationsystem-verilog-assertions
Will
Will

Reputation: 75

How to use $assertoff to disable assertions below a certain level in hierarchy

I want to disable certain assertions in various blocks. These blocks are generated using parameters so their path is not always the same and there may be multiple instantiations of the block (and assertion). Is there a way to 'wild card' the path and all assertions with a certain name?

Note I do not want to disable all of the assertions in the same block only certain ones.

For example replacing:

$assertoff(0, genblk1.a_block.b_block.c_block[0].A_ASSERTION);
$assertoff(0, genblk1.a_block.b_block.c_block[1].A_ASSERTION);
$assertoff(0, genblk3.a_block.b_block.c_block[0].A_ASSERTION);

With something on the lines of:

$assertoff(0, *A_ASSERTION);

Upvotes: 1

Views: 5726

Answers (1)

dave_59
dave_59

Reputation: 42623

You can't use strings or wildcards to access hierarchical paths from within the SystemVerilog language. Most tools provide string access via the command line when disabling certain optimizations. Check your tools User Manual for the equivalent commands.

Upvotes: 0

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