CODEWITHSUNDEEP
makefilewildcard
Luple
Luple

Reputation: 491

Makefile wildcard issue

I am trying to write a makefile to selectively include a certain file.

I have manage to get it working with the following:

OBJS := $(filter-out ./build/./src/class_1.cpp.o, $(OBJS))
OBJS := $(filter-out ./build/./src/class_2.cpp.o, $(OBJS))

OBJS_1 :=./build/./src/class_1.cpp.o $(OBJS)
OBJS_2 := ./build/./src/class_2.cpp.o $(OBJS)

But I would like to make it more generic and use a wildcard.

My understanding is that the following should work:

OBJS := $(filter-out $(wildcard ./build/./src/*), $(OBJS))

I also tried

OBJS := $(filter-out $(wildcard \./build/\./src/*), $(OBJS))

but not sure if the problem is with the special symbols or just a basic understanding.

however it then complains about having too many main functions (class 1 and class 2).

Is there something that I am missing with my understanding of wildcard and filters in make?

If I print out the value of $(OBJS) with the two different approaches, the values are identical, so I am not sure why one solution could work while the other one fails.

However, for some reason OBJS_1 doesn't seem to get the filter that was applied to $(OBJS)

Upvotes: 0

Views: 509

Answers (1)

Matt
Matt

Reputation: 15091

$(wildcard ...) function finds which files actually exist in the filesystem (and some or all .o files might be created during make's execution, thus the result will be different depending on the last command). This is most certainly not what you want.

In your case you need only to perform the string substitution, and the 'match-all' pattern for strings in make is a percent-sign. So it should be:

OBJS:=$(filter-out ./build/./src/%,$(OBJS))

Also note that spaces in the makefile may have significance. For example, $(filter a, b) means that the second argument is " b", not just "b". Even though it wouldn't matter in your case, you should be more cautious with spaces.

Upvotes: 1

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