CODEWITHSUNDEEP
makefilegnu-make
Patrick
Patrick

Reputation: 13

how to avoid variable expansion for a bash for loop in define makefile

Usually, I use foreach call in a makefile. Notwithstanding, I wanted to try different approaches. For that, I have created the code bellow.

I am using GNU Make 3.81 I have replaced the eval by info to understand what is happening. I cannot avoid both the call and the eval expansion to keep the $file

I mean, when I open the file I am getting: "for file in *.v; do echo ; echo ; done; > trial.sh;"

define create_area
$(1): $(2)
    mkdir -p $$(@D); \
    cp -nLr -v $(2)/* $$(@D); \
    cd $$(@D); \
    for file in *.v; do echo $$(file); \
    done; \
    " > trial.sh;

$(foreach a,$(A1) $(A2),\
$(foreach b,$(B1),\
$(eval $(call create_area,$(a),$(b)))))

Thank you in advance,

Upvotes: 1

Views: 563

Answers (1)

Beta
Beta

Reputation: 99172

You're almost there.

If you run the loop in a shell, you must precede the variable name with '$' so that it will be expanded.

If you put that command in a makefile recipe, to prevent Make from expanding the variable name too soon (when the variable has not yet been given a value) you must precede ("escape") that '$' with another '$'.

If you put that recipe in a definition which you will expand with call, you must double each of them:

for file in *.v; do echo $$$$file; done

Upvotes: 2

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