Vivado Behavioral Simulations showing undefined (XX) output

Question

I'm attempting to run a behavioral simulation on my Verilog code in Vivado. However, after the simulation runs, instead of getting outputs, they are shown as red lines with XX, which I believe means they are undefined.

I've attempted to change the timescale at the top of the Verilog files, as shown in Xilinx forum post, but this did not fix my issue.

Here is my Verilog program:

module ctrl(
    input clk,
    input [5:0] A,
    input [5:0] B,
    input [3:0] C,
    output reg [6:0] led
    ); 
    always @(posedge clk)
    begin
        case(C)
            4'b0000:
                //A + B
                led <= A + B;
            4'b0001:
                //A - B
                led <= A - B;
            4'b0010:
                //A++
                led <= A + 1'b1;
            4'b0011:
                //A--
                led <= A - 1'b1;
            4'b0100:
                //B++
                led <= B + 1'b1;
            4'b0101:
                //B--
                led <= B - 1'b1;
            4'b0110:
                //A & B
                led = (A & B);
            4'b0111:
                //A | B
                led = (A | B);                
            4'b1000:
                //A ^ B
                led = (A ^ B);
            4'b1001:
                //~A
                led = {1'b0,~A[5:0]
            4'b1010:
                //~B
                led = {1'b0,~B[5:0]};
            4'b1011:
                //A << B
                led = A << B;
            4'b1100:
                //B << A
                led = B << A;
                
            4'b1101:
                //Light LED[0] if A > B
                if(A > B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;
            4'b1110:
                //Light LED[0] if A < B
                if(A < B)
                    led = 7'b00000001;
                else
                    led = 7'b0000000;
                    
            4'b1111:
                //Light LED[0] if A=B
                if(A == B)
                    led = 7'b0000001;
                else
                    led = 7'b0000000;          
            default: 
                //Unimplemented opcode
                led <= 7'b1111111;
        endcase
    end
endmodule

The testbench

module ctrl_testbench();


    reg[5:0] A;
    reg[5:0] B;
    reg[3:0] C;
    wire[6:0] led;
    
    ctrl dut (
        .A(A),
        .B(B),
        .C(C),
        .led(led)
    );
    
    initial begin
        A = 6'b000001;
        B = 6'b000001;
        C = 4'b0000;
        #100;
        A = 6'b000000;
        B = 6'b000000;
        C = 4'b0000;
        #100;
        A = 6'b000010;
        B = 6'b000010;
        C = 4'b0001;
    end
endmodule

The timing diagram then gives this after the behavioral simulation is run. As you can see A-C (The inputs) are populated correctly, however LED (the output) is red and shows XX.

I'm trying to show the actual outputs.

Answer 1

You need to create a clock signal and drive the clk input of your DUT:

module ctrl_testbench();
    reg[5:0] A;
    reg[5:0] B;
    reg[3:0] C;
    wire[6:0] led;
    reg clk;
    
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    ctrl dut (
        .clk(clk),
        .A(A),
        .B(B),
        .C(C),
        .led(led)
    );

    initial begin
        A = 6'b000001;
        B = 6'b000001;
        C = 4'b0000;
        #100;
        A = 6'b000000;
        B = 6'b000000;
        C = 4'b0000;
        #100;
        A = 6'b000010;
        B = 6'b000010;
        C = 4'b0001;
        $finish;
    end
endmodule

It was convenient for me to create 2 initial blocks. The first never ends due to forever, and the second is necessary to end the simulation with $finish. It is common to separate out distinct functionality using multiple initial blocks.