CODEWITHSUNDEEP
verilog
CODENOOB
CODENOOB

Reputation: 13

How do I fix 'unknown module type error'?

When I run the Verilog code in terminal, it says there is an error in the first line of my code.

num_7seg_B.v:2: syntax error

module num_7seg_B SEG_B(out, w, x, y, z);
    output out;
    input w, x, y, z;
    wire y1;
    wire z1;
    wire y_out;
    wire z_out;
    not G1 (y1, y);
    not G2 (z1. z);
    and G3 (y_out, x, y1);
    and G4 (z_out, x, y, z1);
    or  G5 (out, z_out, y_out, w);
endmodule

Here is test base code:

   module TOP;

   wire w,x,y,z,out;
   reg [3:0] num;
   // instantiation of the module
   num_7seg_B SEG_B(out,w,x,y,z);


   // simulation ends at time 200
   initial #200 $finish;


   // num change from 0 to 15, incremented every 5 seconds
    initial begin
     num=0;
     repeat (15)
    #5 num=num+1; 
   end

   // dump files
   initial
   begin
     $dumpfile("h1_output.vcd");
     $dumpvars;
   end

   // assignment of signals
   assign w=num[3];
   assign x=num[2];
   assign y=num[1];
   assign z=num[0];
   endmodule

Upvotes: 0

Views: 8246

Answers (1)

Adhamzhon Shukurov
Adhamzhon Shukurov

Reputation: 713

Fist of all, a module name cannot contain space.
You can define your module name as:

module num_7seg_B(out, w, x, y, z);

However, using module num_7seg_B SEG_B(out, w, x, y, z); is not an option, since it has space between num_7seg_B and SEG_B.

If you change the module name to module num_7seg_B(out, w, x, y, z);, you will get rid of the syntax error.

You can still use SEG_B as your instance name.

Upvotes: 3

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