CODEWITHSUNDEEP
for-loopverilog
opricnik
opricnik

Reputation: 23

Verilog For loop with no condition gives error: expecting operand

I am using Verilog (not SystemVerilog) and trying to use a for loop with no condition in the middle.

It says "expecting operand".

for(x=5;;x++ ) begin
            led[x] <= 1;

Upvotes: 0

Views: 94

Answers (1)

dave_59
dave_59

Reputation: 42623

Verilog for loop requires a middle condition. Verilog does not have the ++ operator either.

Upvotes: 2

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