CODEWITHSUNDEEP
paginglatency
C. Begley
C. Begley

Reputation: 131

Worst case memory access latency for single level page table

In the worst case, what happens to memory access latency in a virtual addressing environments with a single level page table, with respect to physical addressing?

A - Access time halves.
B - Access time doubles.
C - Access time quadruples.
D - Access time is unbounded.

My guess would be unbounded?

My logic being:.

A single page table can have n-number of entries. To check if the page is there, the MMU would check all entries? So N checks. If not there, it'd page fault, go to where the page is and swap it in somewhere. This would have a latency proportional to the file system the page is stored in and so unbounded?

However I am not really sure.

Upvotes: 0

Views: 445

Answers (1)

C. Begley
C. Begley

Reputation: 131

Figured out the answer from my lecturer:

At best cast, the TLB translates the address and there is one access with the address to get the byte At worst case, the TLB doesn't have the translation, so an access to the page table must be made to get the frame and then another access with this address to get the right byte

Making the access time ~ 2 times as long

Upvotes: 1

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