CODEWITHSUNDEEP
mergevhdlfpga
Chitachi U
Chitachi U

Reputation: 1

VHDL - How to merge two codes together?

I am trying to merge two codes together. One code using the outputs of the previous and converting them to standard logic vector.

I tried to use the process function but it failed

These are the codes

This code is to split the frequency output into 3 different digits for 3 seven segment display ...

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 entity dividerr is
 generic (
 divide_ratio:integer:=1000;
inc    :integer:=256);
 port (
 clckin : in integer range 0 to 256000;
x,y,z : out integer range 0 to 10);
end dividerr;

architecture divider of dividerr is
begin
dividing: process (clckin)
variable div : integer range 0 to divide_ratio;
variable I : integer range 0 to inc;
begin
 if clckin >= 100000 then
div := divide_ratio;
I := clckin/div;
x <= I/100;
y <= (I rem 100)/10;
z <= I rem 10;
elsif clckin >= 10000 or clckin < 100000 then
div := divide_ratio;
I := clckin/div;
x <= 0;
y <= I/10;
Z <= I rem 10;
elsif clckin >= 1000 or clckin < 10000 then
div := divide_ratio;
I := clckin/div;
x <= 0;
y <= 0;
z <= I;
elsif clckin >= 500 or clckin < 1000 then
div := divide_ratio;
I := clckin/div;
x <= 0;
y <= 0;
z <= I * 10;
else I := 0;

end if;
end process dividing;

end divider;

....

This code is to convert the digits to binary before i then convert them again to bcd and map them onto the seven segment displays on the de2 board ...

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity converter is 
port (
x : in integer range 0 to 3;
y,z : in integer range 0 to 9;
xout, yout, zout : out std_logic_vector (7 downto 0));
end converter;

architecture module of converter is   
begin

    xout <= std_logic_vector(to_unsigned(x, xout'length));
    yout <= std_logic_vector(to_unsigned(y, yout'length));
    zout <= std_logic_vector(to_unsigned(z, zout'length));

end module;

Any help would be greatly appreciated.

Upvotes: 0

Views: 1194

Answers (1)

Matthew
Matthew

Reputation: 13957

You need to instantiate your two entities in some higher-level entity, eg:

entity top is
  generic (
    divide_ratio:integer:=1000;
    inc         :integer:=256);
  port (
    clckin           : in integer range 0 to 256000;
    xout, yout, zout : out std_logic_vector (7 downto 0));
end top;

architecture A of top is
  signal x,y,z : integer range 0 to 10;
begin

  INSTANCE1 : entity work.dividerr 
    generic map (
      divide_ratio => divide_ratio,
      inc          => inc)
    port map (
      clckin =>  ,
      x => x,
      y => y,
      z => z);

  INSTANCE2 : entity work.converter  
    port map (
      x => x,
      y => y,
      z => z,
      xout => xout,
      yout => yout,
      zout => zout);

end A;

https://www.edaplayground.com/x/3pJu

Upvotes: 1

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