CODEWITHSUNDEEP
arm
Ken Lin
Ken Lin

Reputation: 1055

Cortex-R5 PMU cycle counter not counting time correctly

I have the PMU configured correctly for PMCCNTR to tick on a Cortex-R5 running FreeRTOS. I will omit the configuration code since it's been repeated on many other StackOverflow questions. I believe the configuration is correctly because I tried running

__asm__ volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr))

periodically, and I was able to see that the pmccntr variable increases monotonically and rolls over after (2^32 - 1).

The CPU is running at 800Mhz, so I expected that if I were to read PMCCNTR in a 1Hz task I would notice that the value increases by 800Mhz. However, the difference in PMCCNTR in between calls to the 1Hz task is more like 72 million. I also tried playing with the 64 clock divider to make sure my observations are sane.

Is my math correct? Or perhaps I am using the wrong number as the CPU frequency? What would be a deterministic way to figure out what frequency the PMCCNTR should be counting at?

Update: The root cause is WFI as @Sean Houlihane pointed out

Upvotes: 1

Views: 1148

Answers (1)

Sean Houlihane
Sean Houlihane

Reputation: 1789

The PMCCNTR does run at core clock, so long as the counter is not disabled and the core isn't in debug state. If you calculate 72 MHz/1.125 MHz then there is a good chance your core is running at external crystal frequency, not from the internal PLL.

The other likely explanation is that the core is in WFI state with clocks stopped for most of the time - in which case the result you measure will be influenced by the amount of work done by the OS.

Upvotes: 1

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