CODEWITHSUNDEEP
intel-fpgaquartus
Sherif AbdelFadil
Sherif AbdelFadil

Reputation: 96

Is there a way to initialize DDR3 memory once without wasting ressources on write-master logic?

I am trying to load 1 GB of data onto DDR3 memory to later use bits of it for on-chip calculations. The data only has to be loaded once and is never altered. I though it might be wasteful(in terms of chip ressources), and definetly complicated for me, to implement a write master interface and a clock crossing bridge for that.

I am hoping there is a way to initialize the DDR3 memory while loading the circuit onto the chip like it is possible with on-chip RAM. I haven't found anything online but I am hoping somebody here can confirm if it's possible or not and possibly how.

I am using Quartus Prime and a Stratix V FPGA.

Upvotes: 0

Views: 398

Answers (2)

mfro
mfro

Reputation: 3345

A chicken-and-egg problem. For DDR3 memory to work properly, you need a working DDR3 memory controller. For that, you'll obviously need your FPGA configuration up and running.

Consequently, you just can't upload your design and the memory contents at configuration time as the DDR3 memory contents would need to be 'parked' somewhere on the FPGA until your memory controller is fully initialized.

You will have to look for some alternative method (e.g loading from an external ROM) after your initial FPGA configuration is finished.

Upvotes: 1

PenguMC
PenguMC

Reputation: 86

Reading or writing to DDR3 memory requires a DDR-controller because it is not a simple operation like for the onchip-memory.

Quartus has a DDR3 SDRAM controller available in the IP library that can be controlled through the avalon bus but it's definitely not simple.

Upvotes: 0

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