CODEWITHSUNDEEP
verilogsystem-verilog
Hisham Hijjawi
Hisham Hijjawi

Reputation: 2415

Does Verilog Module Instantiation Order Matter?

module parity (
a      , // First input
b      , // Second input 
c      , // Third Input
d      , // Fourth Input
y        // Parity  output
);

// Input Declaration
input       a       ;
input       b       ;
input       c       ;
input       d       ;
// Ouput Declaration
output      y      ;
// port data types
wire        a        ;
wire        b        ;
wire        c        ;
wire        d        ;
wire        y        ;
// Internal variables
wire        out_0 ;

wire        out_1 ;

// Code starts Here
xor u0 (out_0,a,b);

xor u1 (out_1,c,d);

xor u2 (y,out_0,out_1);

endmodule // End Of Module parity

Suppose I have the module above. Does the order of the xor module declarations matter? If I reordered the declarations likes so:

xor u1 (out_1,c,d);

xor u2 (y,out_0,out_1);

xor u0 (out_0,a,b);

Would the synthesized circuit be the same?

Upvotes: 0

Views: 1649

Answers (1)

Serge
Serge

Reputation: 12344

The Verilog language is used to describe behavior of connected hardware-like elements and algorithms. The connections define how the elements are evaluated during simulation and how they are synthesized. The simulation scheduling (and hardware behavior) is based on the events which happen in the connection network.

Therefore, the order in which you instantiate those elements is irrelevant, if you connect them right. For example

module a(input i, output o);
endmodule

module b(input i, output o);
endmodule

module top(input i, output o);
  a a1(i, t);
  b b1(t, o);
endmodule

as soon as output of the module a a1 is connected to the input of module b b1, it will behave the same as in here:

module top(input i, output o);
  b b1(t, o);
  a a1(i, t);
endmodule

for readability reasons, you might prefer the first version though.

Upvotes: 1

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